Key Responsibilities
- DevelopSystemVerilog/UVM-basedtestbenches for IP, subsystem, or SoC-level verification.
- Create and maintain verification plans, test cases, and coverage models.
- Implement and integrate scoreboards, monitors, checkers, assertions, and transactors for functional correctness.
- Work with Verification IP (VIP) for industry-standard protocols (AMBA, UCIe, PCIe, DDR, Ethernet, etc.) and integrate them into testbenches.
- Build reusable constrained-random and directed test scenarios.
- Debug failures, perform root cause analysis, and work closely with design and architecture teams.
- Analyze functional coverage, code coverage, and assertion coverage to ensure verification completeness.
- Participate in design/verification reviews and contribute to methodology improvements.
- Automate regression runs and maintain CI verification flows (Jenkins, Git, etc. if applicable).
Required Skills & Qualifications:
- Bachelor’s/Master’s inElectrical/Electronics/ComputerEngineering or related field with 8+ years of experience.
- Strong hands-on experience with SystemVerilog and UVM methodology.
- Proven experience in transactor modeling and VIPintegration/customization.
- Good understanding of digital design fundamentals (RTL, FSMs, buses, etc.).
- Familiarity with coverage-drivenverification andconstraint random test generation.
- Proficiency with industry-standard simulators and/or emulators (Synopsys VCS/Zebu, Cadence Xcelium/Palladium, Mentor Questa/Veloce, etc.).
- Debugging skills using waveforms and verification tools.
- Exposure to SVA (SystemVerilog Assertions) and functional coverage techniques.
- Experience withC/C++/Python fortestbench integration or automation.
- Hands-on work with protocol VIPs (AXI, AHB, APB, UCIe, PCIe, DDR, Ethernet, USB, etc.).
- Strong communication and teamwork skills.
- Experience in applying AI tools forverification/validationis a plus
Experienced HireShift 1 (India)India, Bangalore
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.