In this position, we are looking for a phenomenal engineer to join our world class engineering team to expand the technology that provides us with advantages in programmable solutions.- Responsible for the next generation FPGA and SOC ASIC Implementation flow methodology development.
- Defining, implementing and improving the state of the art AI/ML EDA design solutions by sourcing externally or developing the solutions internally.
- Design Automation Engineers are advocates of applying design methodologies to help execute projects effectively and successfully with high quality.
- Providing consultation and EDA tools support to the multiple projects in the area of Place and Route, Design Synthesis.
- Develop in-house algorithms, scripts, programs to support design activities, EDA tools technology infrastructure setup, CAD wrappers, GUIs, EDA tools customization and automation program
Qualifications- BSEE/MSEE or equivalent in with minimum of 10 years of experience in IC Design or Design Automation.
- Thorough knowledge in physical design flow from RTL to GDS2 and the challenges posed by advanced technologies. This includes detailed understanding of design synthesis, design partitioning, floor planning, place and route, clock tree synthesis and timing analysis.
- Low Power implementation knowledge is a plus
- 5 to 10 years of Physical Design experience with process nodes 20nm, 10nm or below in ASIC/SoC design flows.
- Full familiarity with Synopsys, Cadence or Mentor Graphics physical design tools
- Programming knowledge in Perl, Python, Tcl/Tk, C++, C-shell and other software languages.
- Strong interpersonal skills and good verbal/written communication skills are required.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits