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Facebook ASIC Engineer Design Verification India, Karnataka, Bengaluru 425515786
17.04.2025
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Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
ASIC Engineer, Design Verification Responsibilities
- Develop functional tests based on verification test plan.
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
- Debug, root-cause and resolve functional failures in the design, partnering with the design/arch team.
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
Minimum Qualifications
- Currently has, or is in the process of obtaining a Bachelor's degree in Electronics Engineering, Computer Engineering, Computer Science, VLSI, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
- Experience using constrained-random, coverage driven verification or C/C++ verification.
- Experience in verifying a IP block using standard DV based techniques.
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
- Understanding in at least one of the following areas: computer architecture, CPU, GPU, networking, interconnects, fabrics or similar designs.
Preferred Qualifications
- Currently has, or is in the process of obtaining, a Master’s degree in Electronics Engineering, Computer Engineering, Computer Science or similar technical field.
- Experience in development of SystemVerilog/UVM based verification environments from scratch.
- Experience debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools.
- Experience in verification of any peripheral IPs like UART, SPI, I2C and exposure to protocols like APB, AXI
- Experience working in a CPU/GPU environment.
- Experience with revision control systems like Mercurial(Hg), Git or SVN.
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