Microsoft Design Verification Engineer 

India, Telangana, Hyderabad 

422621693

Design Verification Engineer

• 3 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
• Knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
• Good understanding of computer architecture
• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
• Scripting language such as Python or Perl

The AISoC silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.

• Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
• Develop tests using UVM or C/C++
• Analyse and debug test failures with designers to deliver functionally correct design.
• Identify and write functional coverage for stimulus and corner cases.
• Close coverage to plug verification holes and meet tape out requirements.