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Job Responsibilities
Automation of standard cell design checks and flows
Develop and maintain CAD flows
Interface with CAD and PDK techfile teams to understand requirements and identify opportunities for custom checks and flow updates
Key Requirements
Experience with Virtuoso, Cadence Skill programming, Calibre/ICV preferred
Experience with scripting using Unix, Perl, TCL or Python
Prior experience with large datasets, ML, high volume data analysis
Understanding of analog or standard cell library flows
Understanding of .lib data
Digital or mixed-signal circuit design knowledge
Familiarity with EDA tools used for cell design, layout, verification, simulation and characterization
Qualifications & Experience
Bachelor's in Electrical or Computer Engineering and 8+ years of related experience required
Additional Qualifications
Excellent written and verbal communication skills
Collaborate and work within and across teams
Lead major initiatives to completion with minimal supervision
Compensation and Benefits
The annual base salary range for this position is $107,000 - $171,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
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