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Job Responsibilities
Design standard cells at the transistor level
Simulate and analyze circuit designs
Generate and verify library EDA models
Run regression and other quality checks on library deliverables
Interface with design teams to support their requirements
Key Requirements
Digital or mixed-signal circuit design knowledge
Understanding of cell layout or physical design
Understanding of FinFet, RibbonFet/GAA process nodes
Understanding of verilog, lef , .lib and other industry standard EDA models
Familiarity with EDA tools used in STA and PnR
Experience with .lib syntax including NLDM/CCS/LVF is a plus
Experience with Virtuoso, Cadence Skill programming,scripting using Unix, Perl, TCL or Python is strongly desired
Qualifications & Experience
Bachelor's in Electrical or Computer Engineering and 2+ years of related experience required
Candidates with Masters/PhD preferred
Singapore Citizen/PR only
Additional Qualifications
Excellent written and verbal communication skills
Collaborate and work within and across teams
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