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Key Responsibilities
Conduct detailed studies of chip architecture and microarchitecture to define, develop, and execute comprehensive test plans that thoroughly validate switch features in both emulation phase and post-silicon
Develop system-level tests usingTcl, ITcl, Python, C/C++to verify networking switch chips and systems.
Synthesize Verilog RTL and build models for emulation platforms such asZebuorPalladium.
Debugging Expertise:Perform chip/system-level debugging and root cause analysis for hardware and software issues, effectively addressing Pre/Post Silicon issues and challenges.
Automation and Methodology:Develop and optimize automation scripts and emulation methodologies to enhance efficiency, reusability, and value.
Reusable Components:Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation processes.
Silicon Bring-up:Plan, organize, and execute silicon bring-up and test plans
Environment Management:Create and maintain robust emulation and post-silicon validation environments, supporting a global user community.
Cross-functional Collaboration:
Experience withC/C++ DPI Transactors,SystemVerilog assertions, and coverage metrics.
Proven ability to design and develop synthesizable models for emulation.
Hands-on experience withIXIA/Spirent traffic generatorsfor networking validation.
Strong understanding of networking protocols and RFC test suites.
Familiarity withcommunication/interfaceprotocols like PCIe, SPI, and JTAG.
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