IBM Design Enablement Parasitic Extraction Developer 

United States, New York, City of Albany 

414675081

Your Role and Responsibilities
As the next Design Enablement Parasitic Extraction Developer you will Develop Parasitic Extraction (PEX) decks using industry-standard tools such as Mentor Graphics’ Calibre and Synopsys Star-RC. You will have close and frequent cooperation with process development engineers.

1. Develop Parasitic Extraction (PEX) decks from Process Assumption Specifications and Design Rules. Work closely with process development engineers, device modeling engineers, and design automation engineers

2. Interpret Process Assumption Specifications and Design Rules to create test layouts, using industry standard (EDA) tools such as Cadence Virtuoso Design Environment

3. Debug and solve problems in a team environment
1. Understanding of physical layout, technology groundrules, and semiconductor processing
2. Experience developing automation and scripting
3. Experience using the Cadence Virtuoso or other layout design tool
4. Ability to debug errors, solve problems, and work in a team environment

1. Experience developing Layout vs Schematic (LVS) decks with Mentor Graphics’ Calibre, Synopsys ICV or another industry-standard tool
2. Experience developing Parasitic Extraction (PEX) decks with Synopsys StarRC or another industry-standard tool
3. Experience with advanced sub-micron semiconductor technology nodes
4. Experience with Process Emulation using Synopsys SPX or another industry-standard tool