Analyze and model analog behavior (Verilog-AMS modeling).Ensure specification compliance and correct functionality of attributes defined in the verification matrix.Define checkers and assertions.
Key Qualifications
3+ years hands on experience in analog and mixed signal verification
Knowledge of System Verilog, Verilog-AMS, TCL scripting
Good analog and digital design background to analyze verification results
Scripting language knowledge (Python/Perl) is a plus
Outstanding sense and drive for quality of deliverables
Teammate with excellent written and verbal communication skills
Always enthusiastic to collaborate and take on diverse challenges with international teams
Fluent English skills are mandatory
Education & Experience
MS in Electrical Engineering required or equivalent
Additional Requirements
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