ARM Principal Engineer RTL Design 

India, Karnataka, Bengaluru 

407975624

Responsibilities

• As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team developing Subsystems & SoCs.
• You will work the Architecture team to gather the requirements and develop Micro-architecture specifications for one or more SOC Infrastructure areas such as Power management, Debug, Clocks, Resets.
• Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks.
• You will work with the verification team to review test plans, and help debug design issues.
• You will work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA.
• You will also contribute to developing and enhancing the design methodologies used by the team.
• You will guide and support other members of the team as needed to enable the successful completion of project activities.
• You will balance other opportunities such as working with Project Management on activities, plans, and schedules

Required Skills and Experience:

• In addition to bringing your accomplishment of either Bachelors or Master’s degree or equivalent experience in Computer Science or Electrical/Computer Engineering.
• Experience of 12+ years working in design of complex compute subsystems or SoCs, you will need:
• Expertise in creating Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power management, Debug, Clocks and Resets.
• Strong knowledge of digital hardware design and Verilog HDL.
• A thorough understanding and experience of the current design techniques for complex SoC development.
• Experience leading and developing RTL for Subsystems or SoCs.
• Conversant with Lint, CDC and RDC flows.
• Good communication (written, verbal, presentations) skills.
• Experience with Perl, Python or other scripting language

Desired Skills and Experience:

• Experience with ARM-based designs and/or ARM System Architectures
• Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet
• Experience with SystemVerilog and verification methodologies – UVM/OVM
• Experience leading small teams or projects
• Experience or knowledge in the following areas
• Synthesis and timing analysis
• Static design checks, including CDC, RDC, X-Propagation, Linting
• Power management techniques
• DFT and physical implementation