Job Description- Performs functional verification of IP logic to ensure design will meet specification requirements.
- Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
- Executes verification plans and defines and runs system simulation models to verify the design and uncover bugs.
- Replicates, root causes, and debugs issues in the presilicon environment.
- Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and hardware verification teams to improve verification of complex architectural and microarchitectural features.
- Drives technical reviews of plans and proofs with design and architecture teams.
- Maintains and improves existing functional verification infrastructure and methodology.
- Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
- Technically leads a team of verification engineers to independently drive/deliver IP level verification.
Minimum Qualifications:
- Bachelor’s in engineering with 14+ years of experience in front end verification.
- Design Verification Architect role.
- Must to have Design Verification candidates with UVM expertise
- Concentration on VLSI / IC design
- Prior Exp in IP Verification
- Must have experience Leading multiple IP`s together
- Lead exp required
- Transceiver & Ethernet knowledge will be added advantage
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing BenefitsThis role will require an on-site presence.