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What you will be doing:
Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
What we need to see:
B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
0-2yearsof experience in physical design and/or BE power optimization aspects.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage.
FE design experience is an advantage.
Excellent problem-solving, partnership, and interpersonal skills.
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