Broadcom Package Design Engineer 

United States, California, San Jose 

39975900

RESPONSIBILITIES:

• Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
• Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
• Schedule, prioritize, & track your work across 2+ projects simultaneously
• General flip-chip BGA package design & engineering
• Project management and customer interface for your design projects
• Contribute to efficiency improvements for the design team, through processdevelopment/improvement,automation, documentation, etc.
• Physical design (layout) is a foundational responsibility in this role

EDUCATION/EXPERIENCE & REQUIREMENTS:

• BSEE or similar field and 12+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 10+ years’ work experience
• Knowledge of package-level signal integrity and power integrity, to apply to package designs
• Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
• Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
• Self-management and organization skills
• Preferred candidates will also have 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest

OTHER REQUIREMENTS

• This job requires working on-site at the Broadcom office, 5-days a week. This is not a remote-work position

Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.