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What you'll be doing:
Run integration flows to build RTL, run connectivity checks, and assemble logical units.
Collaborate with front-end teams to resolve connectivity issues and implement design fixes to ensure physically-viable RTL netlists are delivered to downstream physical design flows.
Run synthesis workflows and optimize for area, power, and timing.
Run physical design flow from netlist to GDS, perform STA, physical verification (LVS/DRC)
Perform netlist checks and formal equivalence validation.
Enhance tool automation, streamline workflows, and document best practices.
What we need to see:
BSEE / MSEE or equivalent experience.
Minimum 2+ years of experience in VLSI physical design implementation on 16nm, 7nm, 5nm or 3nm technology.
Able to assist in design flow development and debugging.
Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys(ICC2/DC/PT/STAR/ICV),Cadence(Genus/Innovus/Tempus)and other major EDA companies.
To be successful you should possess strong analytical and debugging skills.
Proficiency using Python, Perl, Tcl, Make scripting is desired.
Great teammate
You will also be eligible for equity and .
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