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Google Senior Lead CPU RTL Engineer United States, Texas, Austin 398308099
20.05.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with RTL language (e.g. SystemVerilog) and related design processes (e.g., Lint, UPF).
Preferred qualifications:
- PhD in Electrical Engineering or Computer Science.
- Experience leading front-end design for modern processor components or AI accelerators.
- Experience with ARM Instruction Set Architecture.
- Experience with SOC design, architect, and integration.
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