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Nvidia Senior Physical Design Methodology Engineer Innovus Flows United States, Texas 396985205
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What you will be doing:
Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes
Develop flows for advanced place and route methods, floorplanning and chip assembly, power and clock distribution, power and area optimization, timing, IR and EM analysis and closure
Work with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all our product lines
What we need to see:
MS in Electrical or Computer Engineering (or equivalent experience)
Minimum 7 years’ experience in Physical Design Engineering
Proven track record of PPA improvement on high performance and low power designs in advanced technology nodes
Strong understanding of physical design optimization and routing methodologies at place, cts, route and postroute, especially power and area efficient setup and hold optimization
Solid background in advanced Clock tree synthesis methods and techniques
Strong background in STA, extraction, timing and RC correlation
Good understanding of design rules in advanced nodes and their impact on DRC closure and PPA optimization
Understanding of power intent files such as UPF, and use of FSDB/SAIFs for power optimization
Understanding of hierarchical design, pinning and budgeting flows
Experience with power distribution networks, Design for Yield and Manufacturability, EM and IR closure and thermal management
Expertise and in-depth knowledge of industry standard EDA tools
Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.
Experience and understanding of AI/ML methods in physical design optimization is preferred
Expertise and in-depth knowledge of industry standard EDA tools,with proficiency in Innovus based flows preferred
You will also be eligible for equity and .
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