Samsung Front-End Infrastructure / CAD Engineer FE Design Verification 

United States, Texas, Austin 

393283769

Role and Responsibilities

The FE Infrastructure/CAD team within Samsung is seeking a highly skilled and motivated Engineer with extensive experience in Front-End (FE) Design Verification flows, tools, and methodologies. This role requires deep technical expertise and experience across multiple verification tools and platforms, as well as a track record of solving complex challenges in FE infrastructure. Candidates should possess a specialized skill set that encompasses regression management, coverage analysis, RTL architecture, tool deployment, and extensive interaction with industry-leading EDA vendors.

• Development & Maintenance of Verification Flows:
• Regression Management & Triage:
  You lead regression management systems, including flow-based regression support. Proactively manage regression triage, interactive user requirements, and troubleshoot issues to ensure seamless project continuity. Expertise in debugging and resolving issues related to coverage, regression fail triaging, and flow stability.
• Advanced Coverage Analysis:
  You demonstrate expertise in coverage tools by actively debugging and resolving intricate coverage-related support and merge issues. Support end-to-end coverage analysis workflows, ensuring accurate data insights for coverage closure.
• EDA Tool & Vendor Management:
  You act as the point of contact for VCS Synopsys issues, providing in-depth debugging, troubleshooting, and solutions to complex problems. Regularly liaise with Synopsys vendors and other EDA partners to coordinate tool support, resolve escalated issues, and stay updated on new developments, maintaining an open line of communication to ensure high-quality support for verification processes.
• RTL Architecture Tool Deployment & Support:
  You successfully deploy and maintain tools for RTL Architecture, ensuring integration with FE verification flows and addressing any support requirements. Provide expert guidance on RTL architectural workflows and deployment best practices.
• Advanced Tool Knowledge & Support:
  You provide specialized support for various verification tools, including VCS and IES with xprop modeling, and work with advanced functionalities like fcov_analyzer. Ensure compatibility across platforms and resolve any tool-specific issues in support of FE verification workflows.
• Version Control Expertise:
  You leverage extensive knowledge of Git.

Skills and Qualifications

• 10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a PhD
• Proven experience in designing, maintaining, and troubleshooting FE Design Verification flows and CAD infrastructure for large-scale, high-performance projects.
• Expertise in flow-based regression management, with strong analytical skills in debugging regression and coverage issues.
• Familiarity with industry-standard tools including Synopsys VCS, IES, and RTL architecture tools, with hands-on experience in xprop configuration for VCS and IES.
• Advanced knowledge of version control systems, particularly Git, Perforce, and Git-P4 interfaces, with an ability to support and streamline versioning workflows.
• Strong communication skills, with experience working directly with EDA vendors to resolve issues and improve tool performance.
• Ability to work independently and as part of a team, with a proactive approach to problem-solving and a strong attention to detail.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.