Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.
Minimum Qualifications
Bachelor's degree in electronic, Electrical, Mechatronic engineer, computer science, or related field of study with 2+ years of experience in:
Programming in Python or equivalent languages (packages, classes, methods and properties), with special attention to performing quick scripting.
VLSI Logic design or verification.
Major EDA tools (e.g., Synopsys VCS/Fusion Compiler/Spyglass, Cadence Conformal/Xcelium, Siemens Mentor Graphics Tessent, etc.)
Unix/Linux and Windows operating systems.
Intermediate English Level.
Good communication skills in a professional environment.
Costa Rican unrestricted work permit.
Preferred Qualifications
System Verilog / OOP, OVM/UVM.SOC-level design/integration and/or validation.
RTL quality checks.
Simulation-based debug (VCS, Verdi, DVE).
Computer (CPU) and/or System (Platform) Architecture.
Object Oriented programming.
Front-end Design TFMs (Tools, Flows, and Methodologies).
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits
