Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience.
5 years of experience in simulating digital reasoning at Register-Transfer Level (RTL) level using SystemVerilog and UVM.
5 years of experience in performance verification for IPs.
Preferred qualifications:
Experience in Caches Hierarchies, Coherency, Memory Consistency Models, Double Data Rate SDRAM/Low Power Double Data Rate SDRAM (DDR/LPDDR), Peripheral Component Interconnect Express (PCIe), Packet Processors, Security, or Clock and Power Controllers.