Broadcom IC Verification Engineer 

United States, California, San Jose 

387902670

Job duties include:

Architect and Develop scalable and reusable Testbench Environment using the framework of Verification Methodologies.

Develop Test plans for all features of the design, conduct reviews, Write Functional coverage for these features.

Build pseudo-random tests to Verify the design and achieve full Functional coverage and stability of Regressions

Debug Regression failures, analyze Functional Coverage gaps and improve Tests to cover the gaps

Lead the documentation of Verification Strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.

Come up with strategies to improveVerification quality and Efficiency

Mandatory Requirements:

Bachelor's degree in Electrical Engineering or related degree and 12+ years related experience or Master's degree in Electrical Engineering or related degree and 10+ years related experience

Decade+ experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing

Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification

Very proficient in System Verilog and Verification Methodologies like UVM

Good debug skills in analyzing regression failures and understanding of complex designs

A good understanding of a layered complex protocols like PCI Express or other multi-layered protocol

These requirements are a plus:

Scripting knowledge of Python or Perl

Comfort with Makefiles

Experience with Verifying with other protocols like AXI

Compensation and Benefits

The annual base salary range for this position is $141,000 - $225,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.