Intel Logic Design Lead 

Israel, Haifa District, Haifa 

385638731

Minimum Qualifications:8+ years of experience in RTL/Logic design on ASICs or FPGA IP blocks or SOCs using Verilog or SystemVerilog RTL codingMust have a BS or MS in Electrical Engineering, Computer Engineering, Computer Science or relatedPreferred Qualifications:Experience with Packet Based Protocols such as USB or PCIe is an advantageDemonstrable experience in logic design and writing RTL in Verilog or SystemVerilogFamiliarity with a range of internal and 3rd-party logic design toolsGate-level understanding of RTL and synthesis - i.e. understand how RTL looks like/behaves after it is synthesized into gates and logic elementsExperience using lab equipment such as logic analyzers, scopes, protocol analyzers and the ability to use them to debug issuesStrong technical leadership, communication and team-work stills.Ability to lead the development in a project with a number of engineers and multiple disciplinesWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits