Intel Physical Design Integration Engineer 

India, Karnataka, Bengaluru 

370247891

Performs integration of cell libraries, functional units, and partitions into subsystems or full chip SoC designs. Conducts the subsystem/full chip layout, integration, verification, and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architectures. Designs, develops, and innovates integration methodologies and flows to improve physical design convergence in domains such as layout, timing, clock tree, formal verification, signal integrity, IO, debug, power routing, noise reduction, reliability, and power and performance. Optimizes design to improve product level parameters such as power, frequency, and area. Collaborates with the design teams during the chip design lifecycle to drive signoff closure for tapeout and meets IP technical and delivery requirements.
Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:

• B.Tech/M.Tech inElectrical/VLSI/Computerscience with relevant experience.

Preferred Qualifications:

• At least 8+ years of experience in physical design/SOC level/SS Top level using industry EDA tools.

• Experience in Python/Perl/TCL programming languages

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (India)India, Bangalore