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* In this position you will use formal verification methods and tools to formally prove the correctness of complicated logic problems.
*Define and lead formal verification architecture.
*Guide and support engineers in the team.
* You will verify unique and complex design blocks against the specification.
* Explore new Formal methods and Tools.
* Collaborating with cross-functional teams, including Design Verification (DV), Architecture (Arch), Design.
* Define assertions and proving design properties, identifying design bugs, and working closely with design teams to improve microarchitecture.
* BSc in Electrical/Computer Engineering or MSc in Mathematics.
* 7+ years of relevant experience.
* Excellent analytical, logical reasoning and problem-solving skills.
* Strong debugging and analytical skills.
* Strong communication and interpersonal skills are required.
Ways To Stand Out From The Crowd
* Formal verification work experience.
* Knowledge of digital logic.
* In-depth knowledge of how Formal works
* Experience in System Verilog/ Verilog/VHDL - Advantage
* Experience in Jasper C - Advantage
* Knowledge in scripting languages such as Python or TCL.
* Knowledge in Industry Standard protocols such as AXI/OCP/APB - Advantage
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