Amazon Sr ASIC Implementation Engineer DBF Silicon 

United States, California, San Diego 

368902843

The Role:
In this role you will:
• As the implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes.
• Work with the ASIC design and DFT teams to understand the design and create timing constraints.
• Check the RTL design for clean synthesis run, perform STA and LEC on netlist.
• Work with RFIC teams to make sure the top level integration of analog blocks are done properly and correct by construction, including formal connectivity checks.
• Work with P&R teams to ensure a smooth hand off of netlists, ensure the timely execution of the P&R responsibilities by that team.
• Participate in flow reviews of all the blocks with the P&R team to ensure that they achieve the best PPA for all blocks.
• Lead the timing sign-off for the post P&R database.
• Ensure that the chip meets the required DFM criteria by verifying the IR/EM results.
Export Control Requirement:

• Bachelor's degree in Electrical / Communications Engineering or related field, or equivalent experience.
• 7+ years of experience in ASIC implementation, i.e., synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or smaller.
• Experience leading or solely developing the methodology and scripts for physical synthesis.
• Proven track record in taping out chips that have gone in to high volume production.
• Familiar with implementing chips that have multiple power islands and power gating.

• Master's or Ph.D degree in Electrical / Communications Engineering.
• 10+ years of experience in ASIC implementation.
• Experience in leading physical design.
• Strong exposure to UPF flow for low power design.
• Strong written and verbal skills
• Experience of working in multi-site/multi-team environment