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What you will be doing:
Responsible for current and next-generation workflow automation for VLSI chip engineers
Design, develop, deploy, and improve highly scalable, long shelf-life workflows and automation platforms for compute and memory-heavy workloads
Deconstruct user workflows into actionable tasks and plan a pathway to automation
What we need to see:
M.S. CS/related (or equivalent experience) with 2+ years developing engineering-facing workflows in an enterprise setting
Solid programming fundamentals in algorithms/data structures with a multi-year history of maintaining platforms in production
EDA / C++ Tools development experience is a plus
Excellent grasp of polyglot systems and the intertwining of workflows and UNIX processes, concurrency and load-balancing
Ways to stand out from the crowd:
Experience seeking and solving problems in partitioning and optimizing existing interconnected systems
Understand NFS and job-scheduling within the constraints of IT-managed LSF infrastructure
Exposure to Perl, Make and VLSI flows, alongside robust design ideals
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