Job Description:This position can be either located in Cambridge or Lund.
Responsibilities:As a verification engineer, you will make a difference by influencing the verification strategy and methodology, taking ownership of complex work packages and driving them to success.
Required Skills and Experience :- Confirmed delivery record in block level verification, using methodologies like UVM.
- Expertise in coverage driven verification of high-complexity designs.
- Experience in the specification, creation, and debug of SystemVerilog/UVM constrained-random testbenches.
- Experience in planning the design process and making realistic effort and time estimates.
“Nice To Have” Skills and Experience :- Experience in working with requirements definition and requirement management.
- Formal verification experience.
- Experience in building C/C++ based models of a microarchitecture.
- Knowledge of the Arm architecture and AMBA bus system.
- Continuous integration platforms such as Jenkins, version control tool git.
- Hands-on experience of machine learning and neural networks.