Microsoft Senior DFT Engineer 

India, Karnataka, Bengaluru 

350003814

Qualifications:

• 5 or more years of experience in DFT/DFD techniques for complex SOCs
• Experience with 3rd party HSIO DFT and verification of SERDES patterns
• Knowledge of IEEE 1687/IJTAG/JTAG
• Knowledge of defect types, fault models, silicon bring-up, debug and validation of DFT features on ATE
• Experience with industry standard simulation, ATPG and MBIST tools, particularly Siemens
• Experience interfacing with DV team supporting DFT patterns for BIST/ICL and Boundary Scan
• Outstanding technical problem solving and debugging ability
• Experience with scripting languages
• Solid communications skills
• Excellent project management skills and ability to juggle multiple projects at once is a plus
• Keywords/Toolsets
• Scan Insertion/Stitching
• Description : Inserts logic to enable DFT testing
• Tools: Fusion Compiler; SiemensTessent
• MBIST
• Description: Memory Built in Self Test
• Tools: Siemens Tessent
• IJTAG/JTAG
• Description: Industry standard designed to assist with device, board, and system testing, diagnosis and fault isolation
• Tools: IEEE1149/1687
• ATPG
• Description: Automatic test pattern generation
• Tools: Siemens Tessent
• GLS
• Description: Gate Level Simulation
• Tools: Synopsys VCS, Siemens Questa

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

You will be part of the design team driving many facets of DFT for large scale silicon designs. The tasks will include understanding of technical requirements and digesting input from various 3party components as well as Microsoft internally developed components. You will need to leverage your experiences to perform DFT-related tasks on several aspects of the program. You will be responsible for scan insertion, scan stitching, memory BIST, JTAG, IO BIST, compression, ATPG patterns, at-speed testing, GateLevel simulations and DFT timing closure of the various design elements.

Throughout the program you will be interacting with various teams, including architecture, verification, physical design, and production/manufacturing ensuring that the design is implemented and verified to the spec.