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Apple RFIC Layout Engineer United States, California, Irvine 343617265
21.04.2025
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Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
As a RF layout engineer, you will be responsible for:- Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.- Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking.- Co-work with designers on block-level and top-level floorplanning.- Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.- Top-level layout integration and verification, schedule management.
- BS and 3+ years of relevant industry experience.
- Good understanding of RC delay, electromigration, and coupling.
- Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (16nm and lower with FinFet experience).
- Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems.
- Excellent communication skills and ability to work with multi-functional teams.
- Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing.
- Solid understanding of RC delay, electromigration, and coupling.
- Understanding of guard rings, DNW, PN junctions, and sophisticated process effects such as LOD, WPE, etc.
- High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology.
- Extensive knowledge of CADENCE layout tools.
- Capability to lead other layout engineers for top-level integration.
- Scripting skills in PERL or SKILL are a plus.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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