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Key job responsibilities
- Manager a team of engineers
- Lead Reviews and forward looking initiatives
- Understand the ASIC design and verification flow
- B.S. In EE/Computer Engineering with 12+ years of experience or M.S. in EE/Computer engineering with 10+ years of experience
- History of leading chips or highly complex subsystems
- Either focused on Verification or Design with a history of first-pass silicon success
- Verilog/System Verilog experience
- 3+ years managing an ASIC DE/DV team with a production tape-out.
- Agile/Scrum experience
- UVM Experience
- EDA Tool Experience - Lint, Formal Equivalent, Synthesys, SDC/UPF
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