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Cisco ASIC Design Engineer Senior Technical Leader United States, California, San Jose 341569968
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The application window is expected to close on: February 10, 2025.
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This role requires being onsite in San Jose, CA 4+ days/week.
Your Impact
- Participate in and contribute to chip architecture definition and discussions.
- Author design specifications and participate in micro-architecture specification reviews.
- Implement Verilog RTL to meet timing and performance requirements.
- Help define, evolve, and support our design methodology.
- Mentor junior engineers on performing project tasks and problem solving.
- Collaborate with the verification team to address design bugs and close code coverage.
- Work closely with physical design team to close design timing and place-and-route issues.
- Perform diagnostic and post silicon validation tests in the lab.
- Work with hardware and software teams to triage and root cause system, software, and customer failures.
Minimum Qualifications
- Bachelor’s degree in Electrical or Computer engineering and 12+ years of ASIC Design experience.
- Verilog/System Verilog programming experience.
- Interactive and waveform debug experience.
- Experience resolving setup and hold timing violations with RTL modification.
- Experience developing micro-architecture solutions and RTL implementation.
Preferred Qualifications
- Master’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience.
- Experience resolving setup and hold timing violations with RTL modification.
- Good written and verbal communication skills.
- Scripting experience (Python, Perl, TCL, shell programming).
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