Amazon Sr Physical Design Engineer - Full Chip Hardware Compute Group 

United States, California, Sunnyvale 

339521536

Work hard. Have fun. Make history.Roles & Responsibilities:- Perform I/O, bump & RDL (redistribution layer) planning, hard IP integration, partitioning, pin and feedthrough planning, repeater insertion, power grid generation.
- Perform special interface, and interconnect planning, bus routing, sequential pipeline planning and top-level design for testability (DFT).
- Be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement.- Drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).
- Supervise and mentor other engineers

- Bachelor’s degree or higher in EE, CE, or CS
- 10+ years or more of practical semiconductor implementation experience
- Scripting experience with Perl, Python, tcl, shell and drive to automate flows
- Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempus
- Must have good communication and analytical skills.
- Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites.

- MS/PhD in Computer Science, Electrical Engineering, or related field
- Experience with memory compiler
- Experience with formal equivalence – Cadence Conformal/Synopsys Formality
- Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification
- Experience with DFT and DFM flows