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Nvidia ASIC Design Engineer BOOT Power Management India, Karnataka, Bengaluru 337263729
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We are now looking for RTL Design engineers for our BOOT and Power management Subsystem Design deployed in Automotive and Client chips. As one of the primary designers, you will be responsible for implementing system BOOT and overall power management architecture of next generation chips. One should possess strong digital design and verification fundamentals.
What you'll be doing:
As a senior designer, be responsible for making architectural trade-offs based onfeature/performance/powerrequirements, analyze system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation.
During the course of a project you would end up driving the following aspects of design for your unit:
Own micro-architecture and RTL development of design modules
Micro-architect features to meet performance, power and area requirements
Work with HW architects to define critical features
Work with verification teams to verify the correctness of implemented features
Partner with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.
What we need to see:
BTech/MTech with 3+ years of experience in crafting complex Units and CPU/micro-controller based Sub-systems
Knowledge of security standards, protocols and system security architectures of modern SOC's would be a significant plus
Excellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams
Good debugging, analytical and problem solving skills
Great interpersonal skills and ability to work as an excellent teammate
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