IBM Thesis Enabling open-source verification flow IBM processors 

Germany, Baden-Württemberg 

337228262

To develop complex microprocessors, multiple hierarchies of the design are being simulated in order to ensure a first-time right design when the first chips are being produced. These complex chips consisting of ASICS and processors incorporate IP as well as standard interfaces. The current IBM verification framework consists of proprietary tools from EDA vendors as well as internal tools. To enable horizontal and vertical reuse across multiple verification levels and components, it is important to base the verification methodology on standards such as Portable Stimulus, languages such as System Verilog but also enabling common programming languages such as Python and C++.

If you’re interested please get in contact with us and include in your response all relevant documents (preferably all in one single pdf file):

1. Cover Letter incl. your availability (earliest start and latest end date)
2. CV incl. your level of German
3. Certificate of enrollment from you university
4. Current transcript of records and other relevant certificates / references
5. Non-EU citizen studying in Germany: copy of passport, residence and work permit
6. Non-EU citizen studying elsewhere: prove of identity incl. place of birth

Required Technical and Professional Expertise

• Study of computer science, electrical engineering or a similar direction
• Good knowledge of programming, knowledge of a scripting language like Python
• Knowledge of Development tools / technologies (e.g. git)
• Good team worker and interest to work in international teams
• Strong abilities in communication in English

First experience in developing hardware, e.g. VHDL or Verilog knowledge