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Apple SoC DRAM Memory Subsystem Validation Engineering Program Manager United States, California, San Diego 336248461
29.06.2024
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Description
• Work on an impactful EPM team responsible for driving technical issue resolution to enable timely silicon to meet daring product schedules.• Make detailed program level plans for memory feature roll-out and align multi-functional teams on the support and validation plans.• Interface and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware and Software.• Drive debug activities in post silicon environments, root-cause problems, and steer the team to the best corrective action to move forward.• Focused issue reporting, bug tracking, organizing and reporting of program risks and status at an executive level.• Plan and lead adoption of DRAM technologies, custom package development and qualification process with multi-functional teams.• Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities.• Attend and drive technical sessions with DRAM vendors on new DRAM technology development to track and follow-up issues/action items and drive vendors to meet spec and schedule requirements.• Work with DRAM GSM and silicon material management teams to plan and track distribution of new DRAM material across all systems in development.• Enable tight collaboration between Design for Test (DFT), Product/Test/QA engineering, SiVal and Systems teams during NPI to finalize SoC performance targets and screen requirements.• Drive internal program process to guarantee high quality silicon execution.
Minimum Qualifications
- BS + 10 years of relevant experience
- Validated SOC/Memory Chip Design, Validation, and Architecture, DRAM Test/Product Engineering experience.
- Experience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management
- Knowledge of high-performance memory subsystem, including SoC memory architecture, sophisticated DDR controller, PHY design and high-speed IO interface, DRAM device, and associated calibration/training mechanisms.
- Excellent debugging skills. Proven track record to drive resolution of critical problems, while under pressure.
- Ability to understand complex technical discussions and extract action plans.
- Passionate to own/drive project development using well-defined metrics.
- Thrives in dynamic schedule driven development environment.
Preferred Qualifications
- Experience shipping high volume DRAMs / SoCs.
- Ability to succinctly summarize complex details for executive reporting
- Extraordinary leadership skills and ability to encourage team members with a commitment to see the bigger picture
- Phenomenal leadership and social skills with a reciprocal approach
- Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $152,400 and $268,200, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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