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You are a dedicated, motivated ASIC emulation/verification engineer to join the team and contribute to the verification of very complex ASICs. You have a Design Emulation background with hands-on experience with emulation platforms like Veloce/Palladium/Zebu. You will be fluent in System Verilog or Verilog to work on the Emulation infrastructure development work.
In-depth knowledge of C++, scripting, as well as ASIC design and verification flow is your strength.
You’ll be part of Cisco Common ASIC Group, focusing on developing and testing various emulation flows and contributing to different aspect of ASIC verification for bug free Silicon.
Responsibilities Include:These jobs might be a good fit