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Apple Early career - SoC Physical Design STA / Timing Engineer F Germany, Bavaria, Munich 331000417
18.07.2024
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Description
Work with Physical Design team, highlighting issues & best practices.Help build timing ECO’s for project tapeout.Build/maintain scripts and methodologies for analysis and runs. You will be responsible for constraints and timing checkups development, including their delivery for synthesis, PnR and signoff STA. Working in parallel on blocks and chip level STA modes.
Minimum Qualifications
- Bachelors's or Master's Degree in a technical field is required.
- General knowledge of the ASIC design timing closure flow and methodology.
- Understanding of STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others.
- Ability to fluently speak and write in English.
Preferred Qualifications
- - General knowledge in timing/SDC constraints generation and management.
- - Proficient in scripting languages (TCL and Perl).
- - Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools.
- - Understand and implement improving existing methodologies and flows.
- - Knowledge in constraint analysis and debug, using industry standard tools as well as backend STA closure is a plus.
- - Familiar with ECO techniques and implementation.
- - Some experience in ASIC timing constraints generation and timing closure. Expertise in STA tools (Primetime) and flow.
- - Familiar with hierarchical design approach, top-down design, timing and physical convergence.
- - Good communication and interaction with Front End teams and Physical Design teams.
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