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Google RTL Design Engineer Multimedia Machine Learning Silicon 
India, Karnataka, Bengaluru 
328765359

31.07.2024
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  • Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques.
  • Experience with a scripting language such as Perl or Python.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs such as Display or Video Codecs.
  • Experience with ASIC design methodologies for clock domain checks and reset checks.
  • Excellent C/C++ programming and software design skills.