Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms.
Creates comprehensive formal verification test and coverage plans to include definition of formal verification scope, strategy, and techniques.
Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques.
Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies.
Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques.
Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.
Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic.
Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures.
Qualifications
M Tech with 7 years of experience / B Tech with 8+ years of experience.
Electrical & Electronics / Communication Engineering
Hands on Experience on verification of IPS / Min 2 years hands on experience on formal verification