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NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.
What you'll be doing:Be part of a cross-business-unit team and own the high-speed IP integration.
Build a Chiplet floorplan layout design from early assembly/planning through implementation and signoff.
Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence.
Define and implement efficient, high-quality Full Chip/Chiplet physical design tools, flows, and methodologies.
Gain hands-on experience implementing the partition-level BE design (RTL2GDS).
B.S. in Electrical Engineering or Electrical Practical Engineer certificate, or equivalent experience.
At least 3 years of relevant experience.
Proven expertise in P&R and Layout tools, TCL scripting, and Netlist-to-GDSII flow.
Great teammate, responsible, and motivated.
Experience in unit and top-level floor planning, full-chip clock tree, power grid planning, and DRC/LVS.
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