Intel DFT Engineer 

India, Karnataka, Bengaluru 

322297259

The Graphics hardware IP team , within the CGAI (Client Compute Group and AI), is responsible for design and development of Graphics, Media and Display IPs as well as discrete Graphics SoCs (GPUs), targeting both Client Device and Datacenter markets. The XSE organization is at the center of Intel's push into the discrete Graphics SoCs (ARC GPUs) market segment targeting next-generation applications such as High-performance computing, Deep learning / training, Cloud Graphics, Media analytics, High-end gaming. In this position you will be part of a world class DFT team which works on next generation SOCs and IPs. You will be working with a group of highly talented engineers working on cutting edge technologies.Candidate will be responsible for DFT design, RTL coding, DFT verification, Array and logic test development, test vector generation and simulation validation, vector bringup on silicon and post-silicon debug.Candidate will be working closely with microarchitects, function design, validation and back-end teams to ensure correct by construct DFT. Post silicon test engineering teams to ensure quick bringup of DFT vectors and help the team through to production.You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant schoolwork, internships, jobs and/or research experience.Minimum skills and Experience:Bachelors in Electrical/Computer Engineering or related field with 1+ years of academic or industry experience. Or a Masters in the same fields with 3+ months of academic or industry experience. Your experience should be in the followingExperience with ASIC design flow (SoC/IP design, integration, or verification)Design automation skills and/or proficiency in programming or scripting languages Preferred Skills and ExperienceAt least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST)Exposure to EDA tools such as ATPG tools, Mentor Tessent shell, Synopsis VCS simulation and/or debug toolsAwareness of Structural design flows, including timing, routing, placement or clocking analysisWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits