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Google Chip Package Signal Power Integrity Engineer United States, California, Sunnyvale 318836081
22.07.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practicalexperience.
- 4 years of experience in chip package SI/PI design for interconnections and advanced package design.
- Experience in post silicon bring up or model correlation.
Preferred qualifications:
- Experience in signal and power integrity for various high speed interconnects (e.g., HBMx, D2D, high speed SerDes, PCIex).
- Experience in programming and data analysis in Matlab, Python, C++ to establish automation flows and data processing.
- Experience with 2.5D/3D package design such as silicon interposer, silicon bridge, 3D die stacking.
- Experience with chip top design, physical design, STA, package, system, validation teams.
- Familiarity with memory testing, next generation memory and chiplet standards and timing budget methodology, including SI/PI co-analysis/design and channel design optimization.
- Understanding of Static Timing Analysis (STA) and voltage budget.
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