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Google Silicon Engineer Design Verification Quantum AI United States, California, Mountain View 315074152
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Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
- Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
- 5 years of experience with design verification.
- Experience verifying digital systems using SystemVerilog/UVM.
- Experience with SoC Verification including CPUs, bus interfaces, or peripherals.
- Experience with scripting languages (such as Python or Perl) for automation and analysis.
Preferred qualifications:
- Experience running DV for mixed-signal ASICs containing analog and RF IP and building mixed-mode models for end-to-end DV coverage.
- Experience with verification strategy definition, verification planning, coverage closure and UVM environment setup.
- Experience with ARM, RISC-V or any processor based DV including tool chains and C-based testing.
- Experience working with functional coverage driven constraint random verification.
- Knowledge of and experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV.
- Knowledge of digital architecture/logic design techniques and principles.
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