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Google Silicon IP RTL Design Engineer India, Karnataka, Bengaluru 312126760
01.12.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel
- Experience in micro-architecture and design of IPs and subsystems
- Experience to ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
Preferred qualifications:
- Experience with scripting languages (e.g., Python or Perl)
- Experience in SoC designs and integration flows
- Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies
- Knowledge of high performance and low power design techniques
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