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Google Physical Design Flow Methodology Engineer 
United States, California, Sunnyvale 
303023825

01.07.2024
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 10 years of experience with EDA tool workflows in semiconductor environments.
  • Experience developing and supporting ASIC physical design flows and methodologies in process nodes.
  • Experience with scripting languages (i.e., Python, Bash, Tcl) for workflow automation and data visualization.

Preferred qualifications:
  • Experience in extraction of ASIC design parameters, QOR metrics, and analyzing trends.
  • Expertise in one or more aspects of physical design implemenation, including 2.5D and 3DIC integration and signoff, IP integration, chip finishing issues.
  • Proficiency in general software engineering principles (data structures, algorithms, profiling, optimization) and object oriented programming languages such as C++.