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Apple CAD Design Verification Methodology Engineer United States, West Virginia 300166120
04.09.2025
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- BS + 10 years’ relevant experience
- Experience developing, maintaining, or enhancing an existing system for regressing RTL.
- Experience debugging vendor tool problems.
- Experience with Python programming
- Experience with TCL or Perl is a plus.
- Experience with interacting with DV team(s) to help solve their problems.
- Experience in implementing new functionality to solve emerging problems or to optimize already existing methods.
- MSEE/CE/CS preferred.
- Knowledge in Verilog and SystemVerilog; familiarity with VHDL a plus.
- Experience with Synopsys VCS, XCelium, or Modelsim.
- Good communications skills are required and prior customer support experience is a plus.
- Experience writing or maintaining a script or Makefile that builds a simulation model from RTL is a plus.
- Familiarity with Verdi and/or Indago is considered a plus.
- Knowledge of C and C++ is a plus.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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