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Intel Reliability Verification Lead India, Karnataka, Bengaluru 299847870
29.04.2025
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Job Description:
- Development, enablement, and deployment of static EOS (electrical overstress) rule decks for Intel Foundry.
- Basic knowledge of PDK and rule deck development is a must.
- Enablement, Validation and Foundry Certifications of Industry Standard EDA Reliability (EM/IR) tools.
- Collaborate with multiple stakeholders to ensure EOS rules are accurately integrated into the design and deployed with PDK. Perform updates and optimizations to the rule deck to accommodate new technology features.
- Troubleshoot and resolve issues related to EOS ruledeck and EM/IR implementation and execution.
- Communicate effectively with stakeholders to provide updates on progress, challenges, and solutions related to EOS HV and EM/IR checks.
- Ensure reliability by performing high-voltage static checks on schematic designs at both the device and template levels, before it gets deployed to customer.
Stay updated with industry trends and advancements in VLSI industry precisely in Reliability domain. - Write good documents for EOS/HV and EM/IR flows and PDK. Train the users and design engineers on EOS/HV and EM/IR flows.
- Self-motivated, strong leadership skills being able to influence across internal and external ecosystem
- Able to work with cross-functional and cross site teams and influence multiple internal and external stakeholders.
- BTech/BE in EE/CE with 7+ relevant industry experience OR MTech/ME in EE/CE with 5+ relevant industry experience in the following areas:
- Basic Reliability concepts like Electro Migration (EM), IR Drop, Temperature Effects.
PVT - EM/IR Inter links, Digital Design Sign off expertise/basic knowledge is essential. - Exposure to minimum of one Digital RV tools in any one major Industry standard EDA Tool (Cadence Voltus/Ansys RHSC) and its working.
- CMOS device physics, process technology and design rules
- Good experience in rule deck development and scripting languages: Python, PERL, TCL
- Good experience in PERC, ERC, SVRF, HV EOS and EM/IR flow methodologies.
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