The point where experts and best companies meet
Google Senior ASIC Design Engineering Silicon India, Karnataka, Bengaluru 298175259
25.02.2025
Share
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 3 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture.
- Experience in handling low power schemes, power roll up and power estimations.
- Experience in Register-Transfer Level (RTL) quality sign-off flows (e.g., CDC, RDC, Lint, Power Intent or LEC).
- Experience with Perl or Python.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
- Experience with methodologies for low power estimation, timing closure, and synthesis.
- Experience with computer architecture.
These jobs might be a good fit
