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Facebook ASIC Engineer Design Verification 
India, Karnataka, Bengaluru 
296439655

14.08.2024
Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.
ASIC Engineer, Design Verification Responsibilities
  • Define and implement block/IP/SoC verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
Minimum Qualifications
  • Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
  • 3+ years hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification
  • Track record of 'first-pass success' in ASIC development cycles
  • 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
  • Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
Preferred Qualifications
  • Experience in development of UVM based verification environments from scratch
  • Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
  • Experience with revision control systems like Mercurial(Hg), Git or SVN
  • Experience with verification of ARM/RISC-V based sub-systems or SoCs
  • Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet
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