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Honeywell Semiconductor Design ASIC/FPGA Trainee / Internship Czech Republic 294645696
22.04.2024
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Key responsibilities
- Digital design (System Verilog / VHDL coding), verification, simulation, synthesis, and static timing analysis
- Integration and Test Support
- Provide Customer Support
- Prepare Documentation
Please note that due to export restrictions, we will only be able to take into consideration applicants with an EU, UK or US citizenship.
Key skills and qualifications
- University level experience in ASIC/FPGA development
- Knowledge or practical experience of VHDL, Verilog or System-Verilog
- Basic knowledge of the ASIC/FPGA design tools: simulators, STA tools, synthesis, etc.
- Intermediate level of English language
- EU or US citizenship
Our offer:
- Opportunity to work on cutting-edge air mobility solutions;
- Working along with a team of highly skilled professionals;
- Flexible working schedule balancing personal, student and professional life.
- JOB ID: req416521
- Category: Engineering
- Location: V Parku 2326/18, budova 10,2.&3.p.,Prague,PRAHA,14800,Czech Republic
- Nonexempt
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