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Job Area:
Interns Group, Interns Group > Engineering Intern
Job description:
Performing Power analysis and power estimation of digital designs (RTL & Gate level)
Performing power optimizations using different techniques and different tools
Supporting Power Aware verification at RTL/Gate level
Define and develop power-intent files (like UPF) for multi-voltage ASIC designs
Perform low power structural validation at RTL/Gate level
Perform Silicon power measurements and analysis
Minimum Qualifications
3rd year in EE studies.
Very Good communication skills (job requires working with multiple different teams).
Very good verbal and written English.
Preferred Qualifications
Knowledge in script writing in Python/Perl/TCL.
Familiarity with Verilog/Sys-Verilog HDL languages.
Familiarity with UNIX development environment.
*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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